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ADuC7060
PROCESSOR REFERENCE PERIPHERALS
INTERRUPT SYSTEM
There are 15 interrupt sources on the ADuC7060 that are con-
trolled by the interrupt controller. All interrupts are generated
from the on-chip peripherals, except for the software interrupt
(SWI), which is programmable by the user. The ARM7TDMI
CPU core recognizes interrupts as one of two types only: a
normal interrupt request (IRQ) or a fast interrupt request
(FIQ). All the interrupts can be masked separately.
The control and configuration of the interrupt system are
managed through a number of interrupt related registers. The
bits in each IRQ and FIQ register represent the same interrupt
source as described in Table 63.
The ADuC7060 contains a vectored interrupt controller (VIC)
that supports nested interrupts up to eight levels. The VIC also
allows the programmer to assign priority levels to all interrupt
sources. Interrupt nesting needs to be enabled by setting the
IRQ
The IRQ is the exception signal to enter the IRQ mode of the
processor. It services general-purpose interrupt handling of
internal and external events.
All 32 bits are logically OR’ed to create a single IRQ signal to
the ARM7TDMI core. The four 32-bit registers dedicated to
IRQ follow.
IRQSIG
IRQSIG reflects the status of the different IRQ sources. If a
peripheral generates an IRQ signal, the corresponding bit in
the IRQSIG is set; otherwise, it is cleared. The IRQSIG bits clear
when the interrupt in the particular peripheral is cleared. All
IRQ sources can be masked in the IRQEN MMR. IRQSIG is
read only.
IRQSIG Register
ENIRQN bit in the IRQCONN register. A number of extra
MMRs are used when the full vectored interrupt controller is
enabled.
Immediately save IRQSTA/FIQSTA upon entering the interrupt
service routine (ISR) to ensure that all valid interrupt sources
are serviced.
Table 63. IRQ/FIQ MMRs Bit Designations
Name:
Address:
Default value:
Access:
IRQEN
IRQSIG
0xFFFF0004
Undefined
Read only
Bit
0
1
2
3
4
Description
All interrupts OR’ed
(FIQ only)
Software interrupt
Undefined
Timer0
Timer1 or wake-up
Comments
This bit is set if any FIQ is active
User programmable interrupt
source
This bit is not used
General-Purpose Timer0
General-Purpose Timer1 or
IRQEN provides the value of the current enable mask. When a
bit is set to 1, the corresponding source request is enabled
to create an IRQ exception. When a bit is set to 0, the corre-
sponding source request is disabled or masked which does not
create an IRQ exception. The IRQEN register cannot be used to
disable an interrupt.
IRQEN Register
5
timer
Timer2 or watchdog
timer
wake-up timer
General-Purpose Timer2 or
watchdog timer
Name:
Address:
IRQEN
0xFFFF0008
6
7
8
9
Timer3 or STI timer
Undefined
Undefined
Undefined
General-Purpose Timer3
This bit is not used
This bit is not used
This bit is not used
Default value:
Access:
0x00000000
Read and write
10
11
12
13
14
15
16
17
18
19
ADC
UART
SPI
XIRQ0 (GPIO IRQ0 )
XIRQ1 (GPIO IRQ1)
I 2 C master IRQ
I 2 C slave IRQ
PWM
XIRQ2 (GPIO IRQ2 )
XIRQ3 (GPIO IRQ3)
ADC interrupt source bit
UART interrupt source bit
SPI interrupt source bit
External Interrupt 0
External Interrupt 1
I 2 C master interrupt source bit
I 2 C slave interrupt source bit
PWM trip interrupt source bit
External Interrupt 2
External Interrupt 3
IRQCLR
IRQCLR is a write-only register that allows the IRQEN register
to clear in order to mask an interrupt source. Each bit that is set
to 1 clears the corresponding bit in the IRQEN register without
affecting the remaining bits. The pair of registers, IRQEN and
IRQCLR, allows independent manipulation of the enable mask
without requiring an atomic read-modify-write.
Rev. 0 | Page 54 of 100
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